Static random access memories (“SRAMs”) have traditionally been implemented using memory cells formed by cross-coupled MOSFET transistors. Each memory cell is coupled to a pair of complementary digit lines by respective access transistors. Thus, each memory cell requires 4 transistors. As a result, SRAM memory cells are relatively large, and they can consume a significant amount of power. Attempts have therefore been made to devise alternative means for implementing SRAM memory cells.
One approach to improving upon existing SRAM memory cell technology is the use of a thyristor as a data storage device. Thyristor-based SRAMs, known as T-RAMs, rely upon the principal that a thyristor, once activated to a conductive state, remains conductive as long as currents are flowing through the thyristor. An example of a T-RAM memory cell 10 is shown in FIG. 1, and its equivalent circuit 10′ is shown in FIG. 2. With reference to FIG. 1, a p-type substrate 12 includes an upwardly projecting pillar 14, which, although not apparent from FIG. 1, preferably has a cylindrical configuration. The pillar 14 is doped in alternating N+, P, N, P+ regions to form a pair of series-connected diodes 20, 22, as shown in FIG. 2. A conductive contact layer 26 (FIG. 1) is deposited on the upper end of the pillar 14, and a bias voltage VB is applied to the contact layer 26. A word line electrode 30 (FIG. 1) is fabricated on, and extends around, the pillar 14 to form a thyristor gate 40 (FIG. 2). The diodes 20, 22 and the thyristor gate 40 form a thyristor 42 (FIG. 2). The above description provides an explanation of one embodiment of the structure of a prior art T-RAM memory cell and is not intended to imply any specific fabrication processing sequence.
With further reference to FIG. 1, the end of the substrate 12 opposite the pillar 14 is doped N+, and a digit line contact 44 is formed on the upper surface of the substrate 12 above the N+ region. Finally, a word line gate electrode 48 is fabricated on the upper surface of the substrate 12 between the digit line contact 44 and the pillar 14. The N+ regions below the contact 44, the N+ region at the bottom of the pillar 14, and the word line gate electrode 48 form an NMOS access transistor 50 (FIGS. 1 and 2). The access transistor 50 couples the thyristor 42 to a digit line 54 (FIG. 2) when the word line WL1 is driven high.
The operation of the T-RAM memory cell 10 shown in FIGS. 1 and 2 can best be explained by reference to a graph showing the electrical characteristics of the thyristor 42. The graph of FIG. 3 shows the current I flowing through the thyristor 42 plotted on the y-axis, and the voltage V across the thyristor 42 plotted on the x-axis. In the portion of the curve in which the current I is greater than IH, the thyristor 42 is ON, i.e., conductive, and the lowest portion of the curve in which the current I is less than IH, the thyristor 42 is OFF, ie., non-conductive. When the thyristor 42 is ON, the current I through it is relatively large, and its resistance, i.e., dV/dI, is relatively low. When the thyristor 42 is OFF, the current I through it is relatively small, and its resistance, i.e., dV/dI, is relatively high.
At a given voltage, V′, the current I can be either a relatively large value I′ (if the thyristor 42 is ON) or a relatively low value I″ (if the thyristor 42 is OFF). Significantly, at this voltage V′, the thyristor 42 will remain ON as long as the current flowing through the thyristor 42 is greater than a holding current IH. Thus, by placing the thyristor 42 in a conductive state and then allowing current to flow through the thyristor 42, the current I will remain above IH. The thyristor 42 thus “remembers” that it has been placed in a conductive state. If the same voltage V′ is placed across the thyristor 42 and the thyristor 42 is placed in a non-conductive state, the current I will remain below IH. The thyristor 42 thus “remembers” that it has been placed in a non-conductive state. In this manner, the thyristor 42 can serve as an SRAM memory cell.
In the memory cell 10′ of FIG. 2, sufficient current flows through the access transistor 50 to maintain the thyristor 42 in a conductive state even though the transistor 50 has been turned OFF. This current, known as the “sub-threshold current” must nevertheless be large enough to maintain the current I through the thyristor 42 above the holding current IH. If the sub-threshold current flowing through the thyristor 42 drops below the holding current IH, the thyristor 42 can switch to the non-conductive state thereby losing the data bit stored in the thyristor 42. It is relatively simple to increase the sub-threshold current through the transistor 50 sufficiently to maintain the current I through the thyristor 42 well above the holding current IH. However, if the current I is maintained at a level significantly above the holding current IH, excess power is consumed, particularly in a high-capacity SRAM containing millions of thyristors. For this reason, it is preferable to maintain the sub-threshold current of the transistor 50 only slightly above the holding current IH.
The sub-threshold current of the transistor 50 can be set to slightly above the holding current IH simply by adjusting the gate-to-source voltage VGS of the transistor 50. However, the sub-threshold current through the transistor 50 at a constant gate-to-source voltage VGS varies as a function of temperature, as shown in FIG. 4. The logarithm of the sub-threshold current is plotted on the y-axis of FIG. 4, and the gate-to-source voltage VGS is plotted on the x-axis for two different temperatures, T1 and T2. At the lower temperature, T1, the current has a magnitude of I1 when the voltage VGS is set to V1. However, at that same voltage V1, the current has a substantially higher magnitude of I2 when the temperature of the transistor 50 has risen to T2. Thus, at a constant voltage V1, the current varies over a range ΔI.
With reference, also, to FIG. 2, if the gate-to-source voltage of the transistor 50, i.e., the difference between the voltage on the digit line 54 and the voltage on the word line WL1, is maintained at a constant value, the sub-threshold current flowing through the thyristor 42 is in its conductive state will vary over a considerable range as the temperature of the thyristor 42 varies. If the voltage VGS is set to provide a sub-threshold current of I′ at a relatively high temperature, the sub-threshold current may drop to below the holding current IH as the temperature of the thyristor 42 is reduced. Under these circumstances, the data bit corresponding to the thyristor 42 being in its conductive state would be lost. As mentioned earlier, this problem could be avoided by simply driving sufficient sub-threshold current through the thyristor 42 to prevent the current from dropping below the holding current IH at any temperature of the thyristor 42. But, doing so would unduly increase the power consumption of memory devices using T-RAM memory cells.
The inability to prevent data loss responsive to temperature variations without unduly increasing power consumption has prevented the widespread use of T-RAM memory cells. There is therefore a need for a solution to these problems, thereby making T-RAM memory devices practical.